As background for our invention, we will review some IBM Technical Disclosure Bulletins, so that the reader can more quickly follow our discussion and understand how our invention differs. Initially, it will be understood that our invention provides a status predictor for a combined shift-rotate/merge unit, utilizes an existing ESA/390 CISC processor with a known predefined instruction set and as such is applicable to the Systems 370-390 in widespread use today by customers of International Business Machines Corporation. Other manufacturer's mainframes also use the IBM known predefined instruction set. Our invention allows the prediction of all shifter status thereby allowing such status to be produced early in the execution of the shift-rotate/merge unit and in parallel with its execution. This early generation of status allows the results of a shift-rotate/merge operation to determine the next microword being fetched during the same cycle that the shift is being executed and the condition code to be set at the end of the shift-rotate/merge unit execution and made available to the branch unit on the subsequent cycle for resolving conditional branches without impacting the machine cycle time of a high performance computer. The status includes that for setting condition codes for all arithmetic and logical shifts, insert character under mask (ICM), and BRANCH-LO conditions of shifter negative and shifter result equal-zero.
International Business Machines Corporation purblishes a Technical Disclosure Bulletin, known as the TDB, to document for the public's information inventions that have been made within the corporation. Turning now to the TDBs in this art, we note that Huffman in TDB 10-89 published a mechanism to produce a mask from a shift amount, or from a pad bit, start bit position and end bit position for controlling the merging of data from a rotator or from an alternative field. The mechanism, however, is not used to derive status, let alone predict status from the inputs, as our invention. The mechanism is only used to control whether bits from the rotator or from the alternative field are to be used as the output from the functional unit.
Losq et al in TDB 06-82 recognize the importance in pipelined processors for resolving condition codes early for branch resolution. They report that CC testing by Branch on Condition (BCs) and Branch on Condition Register (BCRs) test for condition code zero most frequently. Condition code of zero for compares and subtracts indicate that the result is zero. They publish a mechanism for predicting that the outcome will be zero by adding a bitwise compare of the operands for making this determination. They, however, do not consider prediction of shifter-rotate/merge operations.
Huffman et al in TDB 07-89 publish a mechanism for predicting overflow in a shifter. The mechanism, however, does not provide for predicting all shift-rotate/merge unit status such as result equal zero, result less than zero, result greater than zero, left most inserted bit a one, left most inserted bit a zero and not all inserted bits zero, all inserted bits zero as we do.
Dixon et al in TDB 06-78 provide for determining status for operands that are larger than the operands handled by a single functional unit in the data path of a processor by publishing special, duplicate instructions, providing cumulative zero and a non-zero status indicators, and providing latched carry status indicators to remember carries, borrows, or bits shifted from a unit, and a holdover latch to provide inter-instruction status for accumulating status across more than one instruction execution. They, however, to not consider predicting the status in a shifter-rotate/merge unit.
Cannon et al in TDB 06-84 publish a combined ALU/merge unit in which the carry generator is modified such that its output is controlled by a corresponding bit in a mask specifying the merge operation during a merge operation. The sum generator is modified such that its output when in merge mode reflects the status of the corresponding bit in either the A register input to the ALU or the B register input to the ALU, depending on the output from the carry generator. The merged unit allows merging in the ALU without increasing the number of logic stages for a given bookset. Rotation of operands, however, must be done prior to loading in the A or B register inputs to the ALU. Prediction of status for a unit in which shifts as well as rotate/merge operations are supported is therefore not considered.